1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of elevated source and drain structures.
2) Description of the Prior Art
Under current MOSFET technology, raised source/drain regions are used in order to provide a transister having ultra-shallow junctions. Short channel effects increase as the source/drain depth increases, with respect to the gate oxide/silicon substrate interface. In order to minimize the source/drain depth raised source/drain regions are formed, typically using an epitaxial silicon process. The epitaxial growth of raised source/drain regions in MOSFET fabrication gives rise to numerous problems. The epitaxial growth of source and drain regions leaves facets or voids at the interfaces with the spacers formed adjacent to the gate and the interfaces with the field oxide regions. During the salicide process, silicide spikes are formed into these facets causing junction leakage. Another problem with the epitaxial growth of raised source/drain regions is diffusion of junction or lightly doped drain region (LDD) impurities during epitaxial growth. Yet another problem with epitaxial growth of raised source/drain regions is poor robustness and process yield due to difficulty controlling the thickness of the epitaial layer. Finally, the epitaxial growth of raised source/drain regions is an expensive process.
An alternative approach is disclosed by U.S. Pat. Nos. 5,079,180 & 5,198,378 (Rodder), whereby a thin spacer is formed adacent to the gate to allow for ion implant (I/I) after epitaxial growth of raised source/drain regions, while still allowing for sufficient horizontal migration of impurity ions to underlap the gate oxide. These patents also discloses formation of additional spacers in the abovementioned facets. This process does not solve the robustness issue caused by poor control of the thickness of the epitaxial layer nor does it alleviate the expense of epitaxial growth of raised source/drain regions. Also, this process relies on a timed etch in forming the additional spacers, again introducing a robustness issue as this process is also difficult to control.
Another alternative approach is disclosed by U.S. Pat. No. 5,312,768 (Gonzolez), whereby a layer of titanium nitride is deposited over the source/drain regions which acts as a barrier to impurity (phospherous or boron) outdiffusion. However, this process requires additional photo masks and a sputtering process which are expensive and complicated and reduce yields.
Yet another alternative approach is disclosed by U.S. Pat. No. 5,672,530 (Hsu), whereby raised polycrystalline silicon regions are deposited on previously deposited insulating layers, however this process is complicated and expensive due to numerous photo masking and etching steps. Also, the multiple photo masking and etching steps cause control and yield problems.
Alternatively, U.S. Pat. No. 5,641,694 (Kenney) shows a SIO transistor formed in a trench with the source and drain regions on the sidewalls.
U.S. Pat. No. 5,049,515 (Tzeng) shows an EEPROM having a drain region formed in a trench.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the aforementioned US patents.